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74VHC164 8-Bit Serial-In, Parallel-Out Shift Register
August 1993 Revised February 2002
74VHC164 8-Bit Serial-In, Parallel-Out Shift Register
General Description
The VHC164 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC164 is a high-speed 8-Bit Serial-In/Parallel-Out Shift Register. Serial data is entered through a 2input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: fMAX = 175 MHz at VCC = 5V s Low power dissipation: ICC = 4 A (max) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection provided on all inputs s Low noise: VOLP = 0.8V (max) s Pin and function compatible with 74HC164
Ordering Code:
Order Number 74VHC164M 74VHC164SJ 74VHC164MTC 74VHC164N Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names A, B CP MR Q0-Q7 Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) Outputs Description
(c) 2002 Fairchild Semiconductor Corporation
DS011636
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74VHC164
Functional Description
The VHC164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active High Enable for data entry through the other input. An unused input must be tied HIGH. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A * B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.
Function Table
Operating Mode Reset (Clear) Shift MR L H H H H Inputs A X L L H H B X L H L H Outputs Q0 L L L L H Q1-Q7 L-L Q0-Q6 Q0-Q6 Q0-Q6 Q0-Q6
H = HIGH Voltage Levels L = LOW Voltage Levels X = Immaterial Q = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC164
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) DC Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260C
-0.5V to +7.0V -0.5V to + 7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 75 mA -65C to +150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 ns/V 100 ns/V 0 ns/V 20 ns/V 2.0V to 5.5V 0V to +5.5V 0V to VCC
-40C to +85C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0- 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN ICC Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4.0 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 40.0 V A A IOL = 4 mA IOL = 8 mA VIN = 5.5V or GND VIN = VCC or GND V V VIN = VIH or VIL IOH = -4 mA IOH = -8 mA IOL = 50 A V Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max V V VIN = VIH or VIL IOH = -50 A Units Conditions
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA = 25C Typ 0.5 -0.5 Limits 0.8 0.8 3.5 1.5 Units V V V V CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Conditions
Note 3: Parameter guaranteed by design.
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74VHC164
AC Electrical Characteristics
Symbol fMAX Parameter Maximum Clock Frequency VCC (V) 3.3 0.3 5.0 0.5 tPLH tPHL Propagation Delay Time (CP-Qn) 3.3 0.3 5.0 0.5 tPHL Propagation Delay Time (MR-Qn) 3.3 0.3 5.0 0.5 CIN CPD Input Capacitance Power Dissipation Capacitance TA = 25C Min 80 50 125 85 Typ 125 75 175 115 8.4 10.9 5.8 7.3 8.3 10.8 5.2 6.7 4 76 12.8 16.3 9.0 11.0 12.8 16.3 8.6 10.6 10 Max TA = -40C to +85C Min 65 45 105 75 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 15.0 18.5 10.5 12.5 15.0 18.5 10.0 12.0 10 Max Units MHz MHz ns ns ns ns pF pF Conditions CL = 15 pF, RL = 1k CL = 50 pF, RL = 1k CL = 15 pF, RL = 1k CL = 50 pF, RL = 1k CL = 15 pF, RL = 1k CL = 50 pF, RL = 1k CL = 15 pF, RL = 1k CL = 50 pF, RL = 1k CL = 15 pF, RL = 1k CL = 50 pF, RL = 1k CL = 15 pF, RL = 1k CL = 50 pF, RL = 1k VCC = Open (Note 4)
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC.
AC Operating Requirements
Symbol tW(L) tW(H) tW(L) tS tH Minimum Pulse Width (MR) Minimum Setup Time Minimum Hold Time Parameter Minimum Pulse Width (CP) VCC (V) (Note 5) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 tREC Minimum Removal Time (MR) 3.3 5.0
Note 5: VCC is 3.3 0.3V or 5.0 0.5V
TA = 25C Typ
TA = -40C to +85C Guaranteed Minimum 5.0 5.0 5.0 5.0 5.0 4.5 0.0 1.0 2.5 2.5 5.0 5.0 5.0 5.0 6.0 4.5 0.0 1.0 2.5 2.5 Units
ns
ns ns ns
ns
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74VHC164
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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74VHC164
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74VHC164
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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74VHC164 8-Bit Serial-In, Parallel-Out Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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